PCI-SIG Demonstrates PCIe 6.0 Interoperability at FMS 2024

As PCIe 5.0 adoption gains momentum in both data center and consumer markets, PCI-SIG is not sitting idle and is already working to prepare the ecosystem for PCIe specification updates. During FMS 2024, some vendors even talked about PCIe 7.0 with its 128 GT/s capabilities, even though PCIe 6.0 has not yet started shipping. We caught up with PCI-SIG to get an update on its activities and discuss the current state of the PCIe ecosystem.

PCI-SIG has already released the PCIe 7.0 (v 0.5) specifications to its members and expects the full specifications to be officially published in 2025. The goal is to deliver a data rate of 128 GT/s with bidirectional traffic up to 512 GBps using x16 links. Like PCIe 6.0, this specification will also use PAM4 signaling and maintain backward compatibility. Power efficiency as well as silicon die area are also considered as part of the design process.

The move to PAM4 signaling results in higher bit error rates compared to the previous NRZ scheme. This necessitated a different error correction scheme in PCIe 6.0—instead of operating on variable-length packets, PCIe 6.0’s Flow Control Unit (FLIT) coding operates on fixed-size packets to aid in forward error correction. PCIe 7.0 preserves these aspects.

The list of integrators for the PCIe 6.0 compliance program is also expected to be released in 2025, although initial testing is already underway. This was seen in the FMS 2024 demonstration involving Cadence’s 3nm test chip for PCIe 6.0 IP offering along with Teledyne Lecroy’s PCIe 6.0 analyzer. These timelines align well with the specification completion dates and compliance program availability for previous PCIe generations.

We also got an update on the Optics WG – while being optical technology agnostic, the WG also intends to develop technology-specific form factors, including pluggable optical transceivers, embedded optics, packaged optics, and optical I/O. The logical and electrical layers of the PCIe 6.0 specification are being improved to align with the new PCIe optical standardization, and this process will also be carried out with PCIe 7.0 to coincide with the release of that standard next year.

PCI-SIG also has ongoing initiatives around cabling. On the consumer side, we’ve seen significant adoption of Thunderbolt enclosures and external GPUs. However, even data centers and enterprise systems are moving to cabling solutions as it becomes clear that separating components like storage from the CPU and GPU is better for thermal design. Additionally, maintaining signal integrity over longer distances becomes difficult for onboard signal paths. Internal cabling of computer systems can help here.

OCuLink emerged as a good candidate and was fairly widely adopted as an internal link in server systems. It even appeared in some Chinese manufacturers’ mini-PCs in its external consumer-market incarnation, albeit with limited traction. As speeds improve, a widely adopted standard for external PCIe peripherals (or even connecting components in a system) will become a necessity.