Imec and ASML announced that the two companies have printed the first logic and DRAM patterns using ASML’s experimental Twinscan EXE:5000 EUV lithography tool, the industry’s first High-NA EUV scanner. The lithography system achieved resolution sufficient for 1.4nm-class process technology with just one exposure, confirming the system’s capabilities and that the development of the High-NA ecosystem remains on track for commercial chip production by the end of this decade.
“The results confirm the long-awaited ability of High NA EUV lithography to achieve resolution targeting metal layers with a pitch below 20 nm in a single exposure,” said Luc Van den hove, President and CEO of imec. “High NA EUV will therefore be extremely helpful in continuing the dimensional scaling of logic and memory technologies, one of the key pillars that will enable our plans to move deep into the ‘Angstrom era’. These early demonstrations were only possible thanks to the establishment of the ASML-imec joint laboratory, which has enabled our partners to accelerate the introduction of High NA lithography into production.”
The successful test print comes after ASML and Imec spent the past few months preparing the groundwork for the test. In addition to the years it took to build the complex scanner itself, engineers from ASML, Imec and their partners had to develop newer photoresists, primers and reticles. They then had to take an existing production node and tune it for High-NA EUV tools, including performing optical proximity correction (OPC) and fine-tuning the etching processes.
The culmination of these efforts was that, using ASML’s Twinscan EXE:5000 system in the pre-production phase, Imec was able to successfully pattern random logic structures with 9.5 nm dense metal lines, which corresponds to a 19 nm pitch and tip-to-tip dimensions of less than 20 nm. Similarly, Imec also set new feature density records in other aspects, including patterning 2D features at a 22 nm pitch and printing random vias with a center-to-center distance of 30 nm, demonstrating high pattern fidelity and critical dimensional uniformity.
The overall result is that Imec’s experiments have proven that ASML’s High-NA scanner lives up to its intended capabilities, printing features with a resolution good enough to create logic in 1.4nm process technology—all in a single exposure. This last is probably the most important aspect of the tool, since the high cost and complexity of the High-NA tool itself (said to be around $400 million) is supposed to be offset by the ability to fall back to single patterning, which allows for higher tool throughput and fewer steps overall.
Imec didn’t just print logic structures; the group also successfully patterned DRAM designs, printing both the storage node landing pad and the bitline circuit for the memory in a single exposure. As with logic testing, this would allow DRAM designs to be printed in a single exposure, reducing cycle times and ultimately costs.
9.5nm random logic structure (19nm pitch) after pattern transfer
“We are excited to demonstrate the world’s first High NA-enabled logic and memory patterning in the ASML-imec Joint Lab as an initial validation for industrial applications,” said Steven Scheer, Senior Vice President, Computing Technologies and Systems/Scaling Computing at imec. “The results demonstrate the unique potential of High NA EUV to enable single-print imaging of aggressively scaled 2D features, increasing design flexibility, as well as reducing patterning cost and complexity. Looking forward, we expect to provide valuable insights to our patterning ecosystem partners, supporting them in further developing High NA EUV-specific materials and hardware.”
