After Intel’s painful second-quarter earnings call and 2025 cost-cutting plan last week, it’s become increasingly clear that Intel’s future lies in the hands of its foundry group. Between Intel’s IDM 2.0 initiative and its internal chipmaking plans, all roads lead back to Intel regaining—and maintaining—its leadership in manufacturing. To win both as a chip designer and as a contract chipmaker, Intel needs to regain the leadership in manufacturing technology that it once held. In many ways, this is a return to Intel’s classic (and most successful) operating model, but it’s never been this risky for a weakened Intel.
Intel’s fierce race for process leadership means that all eyes will be on the company’s 20A and 18A process nodes for the next 18 months. The final nodes in its ambitious 5-node-in-4-year plan, the 20A/18A twins, are the culmination of several new technologies, most notably Intel’s GAAFET (RibbonFET) implementation, which is being combined with PowerVia, Intel’s backplane power networking (BS-PDN) technology. The 20A is intended to serve as an early version of Intel’s node, while the 18A is intended to serve as an improved version for long-term use both internally and as the first external core node for Intel Foundry. It’s not entirely accurate to say that everything is based on Intel’s 18A, but it’s a small addition.
To that end, we’ll see Intel provide multiple 18A status updates over the next year as it continues to demonstrate to investors and outside customers that the manufacturing side of its business is in order. And today is one of those days, with a new update on the status of 18A.
18A Chips Back & Booting
What’s new in the 18A? The biggest news out of Intel this morning is that their first 18A chips have come back from the development fab and are successfully running operating systems. That means the silicon is not only functional (when powered up), but it’s functional enough to perform basic tasks. That’s a major step in the development of a chip, and at this point Intel wants to make sure the whole world knows about it.
Earlier this year, the company completed the launch of both of its leading 18A chips: Panther Lake for clients and Clearwater Forest for servers. And both chips are launching. This is all the more significant because Clearwater Forest is also based on Intel’s hybrid die-to-die packaging technology, Foveros Direct 3D, where it will also be the lead product for that technology. Which is a promising sign for Intel that not only are their silicon lithography ambitions paying off, but their intention to lead in advanced packaging is also well on their way.
And while Intel doesn’t typically talk about performance this early in the game, it’s interesting that in a separate Q&A this morning with new Intel Foundry boss Kevin O’Buckley, the Foundry Services boss specifically comments that Panther Lake is “performing well.” Similarly, Panther Lake’s DDR memory controller (complex block-mixing logic with PHY) is already running at its target frequency. Progress is going so well that O’Buckley says it’s ahead of schedule on product qualification milestones.
PDK 1.0 released, first external customer release expected in first half of 2025.
As for Intel’s contract foundry operations, the company is now ramping up its efforts as the first full process design kit (PDK) is ready for 18A. Intel released its 18A PDK 1.0 last month, giving Intel customers (and potential customers) the tools to finally finalize their chip designs for production. As is typical with a new node, pre-release PDKs were available for companies to start working on their designs, but PDK 1.0 is typically needed to finalize those designs and align them with formal and finalized process specifications.
For Intel, getting an external PDK for a leading process node is no small feat, since the company has spent decades running its fabs for the benefit of its internal product design teams. A useful PDK for external customers—or, really, a useful fab environment in general—not only requires process nodes that stick to their specifications rather than making custom adjustments, but it means Intel has to document and define all of this in a usable, industry-standard way. One of the major flaws in Intel’s previous efforts to enter the contract foundry business, aside from the fact that they were generally timid efforts, is that they didn’t develop PDKs that external companies could easily use. At the end of the day, Intel wants to attract customers from TSMC and Samsung, and as such, Intel has to provide PDKs that IC designers accustomed to today’s contract fabs can use.
These efforts are finally paying off, albeit slowly. While no names have been revealed yet, Intel expects its first third-party client chip design to be released in the first half of 2025 (H1’25). And, Intel hopes, it will be the first of many.
Ultimately, the hard work of Intel’s foundries isn’t over yet, and it will continue from here. With initial 18A development complete, Intel’s needs are no longer limited to fab R&D, but also to marketing and customer relations. Which, to get back to the beginning of this article, is why Intel is so keen to release 18A status updates: it’s part of a broader effort to entice new customers to try Intel. Even in the best-case scenario, it will take more than a decade to capture a majority of the market for cutting-edge chips. But Intel needs to get that marketing push underway if it wants to get there.
In the meantime, if all goes well for Intel, we should see the first 18A chips released in the second half of the year.
